1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a layout of an internal voltage generating circuit for generating an internal voltage utilized in the semiconductor integrated circuit device. More particularly, the invention relates to the structure of the internal voltage generating circuit suitable to a power supply for a Dynamic Random Access Memory (DRAM) included in a logic-merged memory, in which a semiconductor memory such as a DRAM and a logic are integrated on a single chip.
2. Description of the Background Art
FIG. 47 schematically shows a chip layout of a conventional semiconductor integrated circuit device. In FIG. 47, a semiconductor integrated circuit device 900 includes pads 902 arranged on a periphery of a chip, a DRAM macro 903, and first, second and third merged circuits 905, 907 and 909 arranged in a region surrounded by pads 902. Each of these first to third merged circuits 905, 907 and 909 is formed of, e.g., a logic performing predetermined processing, a Static Random Access Memory (SRAM), a flash memory or the like.
In semiconductor integrated circuit device 900, a hierarchical design method is used. DRAM macro 903, and first to third merged circuits 905, 907 and 909 are designed as macros, respectively, and these macros are arranged on the chip.
DRAM macro 903 has a storage capacity of 32 Mbits, and the input/output data bits are 256 bits (256 I/Os).
With advance of the semiconductor technology, it is now possible to form a logic and a DRAM on a single chip. The DRAM and the logic formed on the same ship are connected merely via internal interconnection lines of small load. Therefore, a data transfer rate between the logic and the DRAM can be made high. Further, the internal interconnection pitch is not affected by a pitch of pads 902, and the internal data bus can have a large bit width so that the band width of data transfer can be increased.
In semiconductor integrated circuit device 900 shown, e.g., in FIG. 47 referred to as a xe2x80x9clogic-merged DRAMxe2x80x9d hereinafter, the contents of processing to be performed by a logic (e.g., first merged circuit 905) changes depending on the application, an therefore the memory capacity required by this logic (e.g., first merged circuit 905) changes. Accordingly, it is necessary to develop a core chip serving as a base, and memories (DRAM macros 903) having storage capacities according to the individual applications must be developed based on the core chip within a short time period.
For implementing the memory arrays having different storage capacities within a short time period, the following approach is most effective: the layouts of the repetition circuits such as the memory cells and associated direct control circuit (array circuit), in which the circuits of the same configuration are repeatedly arranged, such as sense amplifier and address decode circuit, are individually cellulated in advance, and respective cells are arranged in accordance with a practically required storage capacity. Particularly, in the recent years, a CAD (Computer Aided Design) tool such as a module generator, which can automatically perform such arrangement, has been developed. Further, as for other control circuits in the DRAM macro, it is now possible to perform automatic layout and interconnection in accordance with a floor plan similarly to usual logics, so that the layout period can be shortened with less persons.
In DRAMs, internal voltages at various voltage levels are used.
FIG. 48 schematically shows a structure of a circuit generating an internal voltage included in DRAM macro 903. In FIG. 48, internal voltage generating circuitry (power supply circuit) for the DRAM includes an internal power supply circuit 912 for producing an array power supply voltage VCCS from external power supply voltage VEX, an intermediate voltage generating circuit 914 receiving array power supply voltage VCCS to produce intermediate voltages VCP and VBL, and a pump voltage generating circuit 916 receiving external power supply voltage VEX from external power supply node 910, for performing, e.g., a charge pump operation to produce a boosted voltage VPP and a negative substrate bias voltage VBB.
FIG. 49 shows a structure of an array of the DRAM. In FIG. 49, the memory array of the DRAM includes memory cells MC arranged in rows and columns, word lines WL arranged for the respective memory cell rows. Bit line pairs BL and /BL are arranged corresponding to the columns of memory cells MC, respectively. Memory cell MC includes a capacitor MQ for storing information, and an access transistor MT for connecting memory capacitor MQ to bit line BL (or /BL) in response to the potential on word line WL.
Bit line pair BL and /BL is provided with a bit line equalize circuit BEQ for precharging bit lines BL and /BL to intermediate voltage VBL level when made active, and a sense amplifier circuit SA for transmitting array power supply voltage VCCS onto bit line at a higher potential of paired bit lines BL and /BL when made active.
Word line WL is driven to boosted potential VPP level when selected. Substrate bias voltage VBB is applied to a back gate of access transistor MT. Intermediate voltage VCP is applied to one electrode (cell plate electrode) of memory cell capacitor MQ.
As shown in FIGS. 48 and 49, a power supply interconnection line of a large width for supplying an array power supply voltage as well as voltage transmission lines of relatively large widths for transmitting internal voltages VCP, VBL, VPP and VBB are disposed in a portion for generating internal voltages for the DRAM. In the memory array of DRAM, signal lines are set to various voltage levels.
Internal power supply circuit 912, intermediate voltage generating circuit 914 and pump voltage generating circuit 916 produce voltages at required levels in accordance with a reference voltage or a reference current. These reference voltage and reference current are always consumed after power-on. For reducing the power consumption, the circuit producing the reference voltage as well as the circuits supplied with the reference voltage are configured to consume a sufficiently small current, and the current drive capabilities of these reference current supply circuit and reference voltage generating circuit are sufficiently reduced. Therefore, the signal lines transmitting the reference current and the reference voltage are driven by small driving capabilities, and therefore are susceptible to noises applied from other signal lines or the substrate.
For verifying the layout of the above internal voltage generating circuitry, EDA tools such as layout reference check (DRC: Design Rule Check) usually performed and match verification (LVS: Layout Versus Schematic) between schema (logical description of layout) and layout are employed, but stable operations are insufficiently ensured in many cases. Under present circumstances, therefore, it is required to perform, by a skilled engineer, a minute and precise layout work with sufficient measures taken against noises and sufficient margins. In such a power supply circuit (internal voltage generating circuitry) layout, it is necessary to review or reconsider the power supply interconnections as well as the layout for achieving a sufficient immunity against noises and an optimum current supply capability when a floor plan changes in accordance with a storage capacity of the memory. This complicates the design, and impedes reduction in layout period.
For flexible conformance with various storage capacities, a method of utilizing a module structure is proposed by T. Watanabe et al., in xe2x80x9cA Modular Architecture for a 6.4-Gbyte/s, 8-Mb DRAM-Integrated Media Chipxe2x80x9d, IEEE Journal of Solid State circuits, Vol. 32, No. 5, pp. 635-641, May 1997. Watanabe et al. handle an expandable bank, a main amplifier for data reading and a voltage generator as one macro. According to the structure of Watanabe et al., the voltage generator has a fixed structure independent of a storage capacity of the memory, and consideration is not given to change in the power supply circuit structure associated with change in I/O structure, refresh period and page size. In the case of utilizing the above macro, therefore, it is necessary to determine the current supply capability of the voltage generator based on the expected maximum current consumption of the macro. If the storage capacity is small, the voltage generator having the current drive capability exceeding the necessary capability may be used, leading to a problem that an unnecessarily large current is consumed.
A floor layout method in which a storage capacity is expandable is disclosed by T. Yabe et al., in xe2x80x9cA Configurable DRAM Macro Design for 2112 Derivative Organizations, to be Synthesized Using a Memory Generatorxe2x80x9d, ISSCC 98 Digest, pp. 72-73, February, 1988. Yabe et al. have disclosed an arrangement plan of power supply circuitry in the DRAM macro. However, one voltage generator is arranged for each reference array of 1 Mbit for supplying a necessary current to the corresponding 1-Mbit array. However, in each of the case where one bank has a storage capacity of 1 Mbit and the case where one bank has a storage capacity of 8 Mbit, the same number of word lines are activated in one bank so that the same amount of current is consumed in the array. In the case where one bank has 8-Mbit storage capacity, the voltage generators having the current supply capability which is eight times greater than the required current supply capability is used, because the voltage generator is provided for each block of 1 Mbits according to the structure of Yabe et al. This results in a large loss of area.
An object of the invention is to provide a semiconductor integrated circuit device including an internal voltage generating circuit (internal power supply circuit) easily adaptable to change in structure and/or operation condition.
Another object of the invention is to provide a logic-merged memory with an internal voltage generating circuit easily adaptable to change in storage capacity and/or operation condition.
Still another object of the invention is to provide a structure and an arrangement structure of layout of a power supply circuit which allow easy and short time re-design/rearrangement of a power supply related circuitry conventionally difficult in re-designing in a short period with the optimum layout area and the optimum capability.
Briefly, according to a semiconductor integrated circuit device of the invention, for an internal power supply circuit generating an internal voltage used by an internal circuit, a circuit required to supply a large amount of current when the internal circuit operates is formed into a cell with reference (basic) capability as an active unit. The active units of a required number are arranged depending on a magnitude of the current consumption of the internal circuit.
More specifically, the semiconductor integrated circuit device according to the invention includes an internal circuit for implementing a predetermined function, and a power supply circuit having a capability of supplying to the internal circuit a current consumed by the internal circuit when the internal circuit is active, and supplying a predetermined voltage to the internal circuit. The power supply circuit includes active units of a number corresponding to the current consumption capability of the internal circuit, and the active unit has a layout to have a predetermined current supply capability, is formed into a cell, and generates the predetermined voltage.
The internal voltage generating circuit having the reference capability is formed into a cell as an active unit and capability of the predetermined voltage generating circuit can be optimized by arranging the active units of the required number depending on the consumed current amount of the internal circuit. Further, the area loss does not occur.
It is merely necessary to arrange the cellulated active units, and re-design and re-arrangement of the predetermined voltage generating circuit (power supply circuit) can be performed easily within a short time period without requiring entire redesigning of the predetermined voltage generating circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.